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Fully Enumerated Filter Implementation Details
User Input
To CoreFIR Input
Figure 17 · Optional Input Registers
Inter-Column/Row Pipelines
CoreFIR implements several HW architectures, depending on the user configuration. All of them utilize the
transposed architecture shown in Figure 6 .
The hard MACs on a chip are organized into physical columns or rows. Within a column or row, the adder
chain runs on a dedicated resource thus providing excellent performance characteristics. When a filter
utilizes more than one hard MAC physical column or row, the long data path between the columns
introduces an extended propagation delay. To eliminate this critical path, CoreFIR automatically infers
optimal number of fabric pipeline registers in the inter-column or row sections of the adder chain.
Simultaneously, it infers fabric registers in other data paths, which are necessary to preserve the correct
functionality of the filter.
Figure 18 on page 21 presents an example of the two fabric inter-column or row registers in the adder chain
balanced by a pair of the data bus registers. The added registers are shaded in Figure 18 .
Physical column k
Physical column k+1
C(i+4)
C(i+3)
C(i+2)
C(i+1)
C(i)
Figure 18 · Transposed Architecture with Inter-Column Fabric Registers
Fully Enumerated Filter Latencies
The filter imposes the following two latency types:
? Pipeline Latency
? Transition Latency, which is proportionate to the number of filter taps
The overall latency is a sum of these two latency types.
Pipeline Latency
This latency accounts for a time period between a valid input and valid output samples. Figure 19 on page
22 shows the latency when the input registers are disabled. If these are enabled, the pipeline latency adds
up to two clock cycles. The DATAO_VALID flag marks the valid output samples.
CoreFIR v8.5 Handbook
21
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